Accelerating chip design.

Most EDA tooling was built decades ago, under assumptions very different from modern computing. Their arcane user experience requires extensive scripting to get work done.

EDA vendors aren't incentivised to build simpler tools since they can charge to set up and provide you with an environment that just works.

We are changing this with performant, user-friendly tools so you can spend time on your design instead of endless Tcl / Python scripting to orchestrate workflows.

TinyEDA Studio is an integrated digital ASIC design environment. It massively accelerates the physical design process, improves performance, power, and area (PPA) results, and makes it easier to trace design errors back to original RTL.

Faster, simpler tools

• Faster algorithm implementations for macro placement, place and route, static timing analysis and signoff DRC checks.
• GPU acceleration for massively parallel workloads and SIMD/vector compute for CPU workloads.
• Well-designed APIs eliminating glue code between tools.

Design IP

We will use these tools internally alongside automated schematic, layout, and simulation tooling to create digital / analog design IP for:

1. Automotive
2. Aerospace (radiation hardened)
3. Consumer electronics
4. Industrial automation
5. Medical
6. Nuclear (radiation hardened)

Can I run this locally?

Yes. We will have local apps for MacOS, Windows, and Linux, as well as a collaborative web app hostable on-premise.

How difficult is it to switch from my existing EDA suite?

We will provide tooling to port your Tcl scripts and tool-specific configurations, making the switch painless and inexpensive for your organization.

Why should we trust your tool?

We will formally verify equivalence where applicable and work closely with foundries to qualify our tools as signoff-ready.